65nm CMOS Breakthrough: How This Compact Filter Solves the Sub-THz Selectivity Puzzle

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The race for terabit-per-second data rates is pushing wireless systems into the sub-terahertz realm. As spectrum congestion tightens in lower bands, engineers face a physical wall. Traditional passive components simply cannot keep up with the demands of these high frequencies. The solution lies in on-chip integration to eliminate packaging parasitics and boost reliability. Yet, standard CMOS technology struggles here. Lossy silicon substrates and dense metal stacks degrade the quality factors of essential inductors and capacitors. This creates a significant bottleneck for high-speed communication.

Researchers have now introduced a novel bandpass filter designed specifically for 65 nm CMOS technology. This design uses a stub-loaded dual-mode resonator architecture to achieve exceptional frequency selectivity without increasing the circuit area. Conventional methods often rely on complex numerical even-odd-mode analyses. This new approach offers something different. It introduces an LC equivalent-circuit model that provides closed-form pole and zero analysis. This mathematical clarity allows engineers to precisely control transmission zeros. These zeros are critical for sharpening the transition between the passband and stopband.

The core innovation involves a cross-coupled topology that places transmission zeros directly within the initial passband. By reusing the SLR arms for cross-coupling instead of adding dedicated structures, the design reduces the area cost typically associated with high-selectivity filters. The resulting prototype operates at a center frequency of 178 GHz with a fractional bandwidth of 25%. Measured results show an insertion loss of just 5.0 dB. The shape factor reaches an impressive 0.51, indicating a very steep transition from the passband to the stopband.

This filter occupies a minuscule core chip area of 0.129 by 0.273 mm². Normalized to only 0.0124 lambda squared, this compact footprint makes it highly suitable for System-on-Chip platforms. It enables the integration of frequency-division duplexers, image-band suppression in radiometers, and noise reduction in imaging systems. While lumped-element filters struggle above 100 GHz due to degraded capacitor quality factors, and other distributed filters often sacrifice selectivity for size, this design strikes an optimal balance. It outperforms many state-of-the-art CMOS and BiCMOS entries in terms of shape factor while maintaining a competitive absolute area. This advancement marks a significant step forward in making high-speed, high-integrity sub-terahertz communications viable within standard semiconductor manufacturing processes.